The present invention relates to a clock generation circuit, a display device drive circuit, and a control method of the clock generation circuit, and in particular to a clock generation circuit, a display device drive circuit, and a control method of the clock generation circuit for generating a recovery clock from an embedded signal in which a clock is superimposed on data.
In recent years, in a high-speed serial I/F, a data transmitting/receiving method has widely spread in which a transmitting side transmits an embedded signal where a first clock of serial data is embedded in data and a receiving side extracts edge information of the first clock of the serial data from the received embedded signal, samples data by a recovery clock (reproduction clock) restored from the extracted edge of the first clock, and restores the original serial data.
In a receiving circuit of such a high-speed serial I/F, a DLL (Delay Locked Loop) is used to generate a recovery clock for extracting data on the basis of an inputted embedded signal.
As a clock generation circuit that uses a DLL, for example, Patent Documents 1 to 3 are known. The embedded signal is not described in Patent Documents 1 to 3.
[Patent Document 1]
    Japanese Unexamined Patent Publication No. 2010-21706[Patent Document 2]    Japanese Unexamined Patent Publication No. 2009-278528[Patent Document 3]    Japanese Patent No. 3945894